04.09.2024, 10:20:07
Beta-Multiplier Bandgap OTA
OTA for Beta-Multiplier Bandgap.
🔗 Schematics
LVS
LVS-state: Netlists match uniquely.
🔗 LVS-report
SPECIFICATIONS
AC Open-Loop Specification
Parameter |
Min (Spec. / Sim.) |
|
Max (Sim. / Spec.) |
Unit |
Checks (total/pass/fail/NaN) |
Comment |
Open-Loop Gain |
90 / 96.36 |
|
96.433 / 110 |
dB |
5/100.0%/0.0%/0.0% |
Gain at 1Hz |
Phase Margin |
60 / 95.784 |
|
99.199 / 110 |
deg |
5/100.0%/0.0%/0.0% |
Open-Loop |
Unity-Gain Bandwidth |
25.0 / 62.415 |
|
86.608 / 110.0 |
MHz |
5/100.0%/0.0%/0.0% |
|
3-dB Bandwidth |
0.1 / 0.439 |
|
0.56 / 10.0 |
kHz |
5/100.0%/0.0%/0.0% |
|
AC Open-Loop Specification (Monte Carlo)
Parameter |
Min (Spec. / Sim.) |
|
Max (Sim. / Spec.) |
Unit |
Checks (total/pass/fail/NaN) |
Comment |
Open-Loop Gain |
90 / 96.292 |
|
96.502 / 110 |
dB |
1250/100.0%/0.0%/0.0% |
Gain at 1Hz |
Phase Margin |
60 / 93.015 |
|
103.073 / 110 |
deg |
1250/100.0%/0.0%/0.0% |
Open-Loop |
Unity-Gain Bandwidth |
25.0 / 56.509 |
|
98.586 / 110.0 |
MHz |
1250/100.0%/0.0%/0.0% |
|
3-dB Bandwidth |
0.1 / 0.417 |
|
0.588 / 10.0 |
kHz |
1250/100.0%/0.0%/0.0% |
|
CMRR/PSRR Specification
Parameter |
Min (Spec. / Sim.) |
|
Max (Sim. / Spec.) |
Unit |
Checks (total/pass/fail/NaN) |
Comment |
CMRR at 10Hz |
50 / 91.297 |
|
91.772 / 150 |
dB |
5/100.0%/0.0%/0.0% |
|
CMRR at 10MHz |
35 / 67.323 |
|
74.71 / 90 |
dB |
5/100.0%/0.0%/0.0% |
|
PSRR+ at 10Hz |
40 / 94.54 |
|
96.426 / 130 |
dB |
5/100.0%/0.0%/0.0% |
|
PSRR+ at 10MHz |
35 / 52.774 |
|
53.046 / 70 |
dB |
5/100.0%/0.0%/0.0% |
|
PSRR- at 10Hz |
40 / 84.474 |
|
84.821 / 120 |
dB |
5/100.0%/0.0%/0.0% |
|
PSRR- at 10MHz |
5 / 9.985 |
|
11.755 / 20 |
dB |
5/100.0%/0.0%/0.0% |
|
CMRR/PSRR Specification (Monte Carlo)
Parameter |
Min (Spec. / Sim.) |
|
Max (Sim. / Spec.) |
Unit |
Checks (total/pass/fail/NaN) |
Comment |
CMRR at 10Hz |
50 / 65.011 |
|
96.201 / 150 |
dB |
1250/100.0%/0.0%/0.0% |
|
CMRR at 10MHz |
35 / 62.839 |
|
82.439 / 90 |
dB |
1250/100.0%/0.0%/0.0% |
|
PSRR+ at 10Hz |
40 / 63.382 |
|
98.312 / 130 |
dB |
1250/100.0%/0.0%/0.0% |
|
PSRR+ at 10MHz |
35 / 51.743 |
|
55.696 / 70 |
dB |
1250/100.0%/0.0%/0.0% |
|
PSRR- at 10Hz |
50 / 82.994 |
|
87.714 / 120 |
dB |
1250/100.0%/0.0%/0.0% |
|
PSRR- at 10MHz |
5 / 10.005 |
|
11.889 / 20 |
dB |
1250/100.0%/0.0%/0.0% |
|
Output Range Specification
Parameter |
Min (Spec. / Sim.) |
|
Max (Sim. / Spec.) |
Unit |
Checks (total/pass/fail/NaN) |
Comment |
Negative Output Bound |
-2.5 / -2.263 |
|
-2.253 / -2 |
V |
5/100.0%/0.0%/0.0% |
|
Positive Output Bound |
2 / 2.098 |
|
2.124 / 2.5 |
V |
5/100.0%/0.0%/0.0% |
|
Output Range Specification (Monte Carlo)
Parameter |
Min (Spec. / Sim.) |
|
Max (Sim. / Spec.) |
Unit |
Checks (total/pass/fail/NaN) |
Comment |
Negative Output Bound |
-2.5 / -2.264 |
|
-2.251 / -2 |
V |
1250/100.0%/0.0%/0.0% |
|
Positive Output Bound |
2 / 2.094 |
|
2.126 / 2.5 |
V |
1250/100.0%/0.0%/0.0% |
|
Parameter |
Min (Spec. / Sim.) |
|
Max (Sim. / Spec.) |
Unit |
Checks (total/pass/fail/NaN) |
Comment |
Positive CM Input Bound |
0.8 / 0.905 |
|
1.074 / 1.5 |
V |
5/100.0%/0.0%/0.0% |
Input transistor sat. |
Parameter |
Min (Spec. / Sim.) |
|
Max (Sim. / Spec.) |
Unit |
Checks (total/pass/fail/NaN) |
Comment |
Positive CM Input Bound |
0.8 / 0.89 |
|
1.085 / 1.5 |
V |
1250/100.0%/0.0%/0.0% |
Input transistor sat. |
Slew-Rate/Offset Specification
Parameter |
Min (Spec. / Sim.) |
|
Max (Sim. / Spec.) |
Unit |
Checks (total/pass/fail/NaN) |
Comment |
Input Offset |
-0.0 / 0.0 |
|
0.0 / 0.0 |
mV |
5/100.0%/0.0%/0.0% |
|
Slew-Rate (Positive) |
10.0 / 15.989 |
|
20.198 / 30.0 |
MV/s |
5/100.0%/0.0%/0.0% |
|
Slew-Rate (Negative) |
-30.0 / -21.782 |
|
-17.249 / -10.0 |
MV/s |
5/100.0%/0.0%/0.0% |
|
Slew-Rate/Offset Specification (Monte Carlo)
Parameter |
Min (Spec. / Sim.) |
|
Max (Sim. / Spec.) |
Unit |
Checks (total/pass/fail/NaN) |
Comment |
Input Offset |
-10.0 / -2.675 |
|
3.155 / 10.0 |
mV |
1250/100.0%/0.0%/0.0% |
|
Slew-Rate (Positive) |
10.0 / 15.515 |
|
20.268 / 30.0 |
MV/s |
1250/100.0%/0.0%/0.0% |
|
Slew-Rate (Negative) |
-30.0 / -21.927 |
|
-17.13 / -10.0 |
MV/s |
1250/100.0%/0.0%/0.0% |
|
Noise Specification
Parameter |
Min (Spec. / Sim.) |
|
Max (Sim. / Spec.) |
Unit |
Checks (total/pass/fail/NaN) |
Comment |
Input Noise at 10Hz |
0.0 / 0.943 |
|
1.032 / 10.0 |
uV/sqrt(Hz) |
5/100.0%/0.0%/0.0% |
|
Input Noise at 10MHz |
0.0 / 0.046 |
|
0.05 / 1.0 |
uV/sqrt(Hz) |
5/100.0%/0.0%/0.0% |
|
THD Specification
Parameter |
Min (Spec. / Sim.) |
|
Max (Sim. / Spec.) |
Unit |
Checks (total/pass/fail/NaN) |
Comment |
THD |
0 / 0.1 |
|
0.13 / 0.3 |
% |
5/100.0%/0.0%/0.0% |
|
THD Specification (Monte Carlo)
Parameter |
Min (Spec. / Sim.) |
|
Max (Sim. / Spec.) |
Unit |
Checks (total/pass/fail/NaN) |
Comment |
THD |
0 / 0.094 |
|
0.144 / 0.3 |
% |
1250/100.0%/0.0%/0.0% |
|
AC Open-Loop Specification [PEX]
Parameter |
Min (Spec. / Sim.) |
|
Max (Sim. / Spec.) |
Unit |
Checks (total/pass/fail/NaN) |
Comment |
Open-Loop Gain |
90 / 96.356 |
|
96.43 / 110 |
dB |
5/100.0%/0.0%/0.0% |
Gain at 1Hz |
Phase Margin |
60 / 60.561 |
|
65.715 / 110 |
deg |
5/100.0%/0.0%/0.0% |
Open-Loop |
Unity-Gain Bandwidth |
25.0 / 45.572 |
|
56.489 / 110.0 |
MHz |
5/100.0%/0.0%/0.0% |
|
3-dB Bandwidth |
0.1 / 0.435 |
|
0.553 / 10.0 |
kHz |
5/100.0%/0.0%/0.0% |
|
AC Open-Loop Specification (Monte Carlo) [PEX]
Parameter |
Min (Spec. / Sim.) |
|
Max (Sim. / Spec.) |
Unit |
Checks (total/pass/fail/NaN) |
Comment |
Open-Loop Gain |
90 / 96.271 |
|
96.487 / 110 |
dB |
1250/100.0%/0.0%/0.0% |
Gain at 1Hz |
Phase Margin |
60 / 55.687 |
|
69.255 / 110 |
deg |
1250/89.6%/10.4%/0.0% |
Open-Loop |
Unity-Gain Bandwidth |
25.0 / 41.77 |
|
63.079 / 110.0 |
MHz |
1250/100.0%/0.0%/0.0% |
|
3-dB Bandwidth |
0.1 / 0.416 |
|
0.58 / 10.0 |
kHz |
1250/100.0%/0.0%/0.0% |
|
Show specification violation details...
FAIL: Specification violation for parameter "Phase Margin":
FAIL: group:ff_mm file:work/sim/bmbgota/bmbgota_tb.1_bmbgota_ext/batch_4/ff_mm/ac_ol.csv Index:1
FAIL: group:ff_mm file:work/sim/bmbgota/bmbgota_tb.1_bmbgota_ext/batch_4/ff_mm/ac_ol.csv Index:3
FAIL: group:ff_mm file:work/sim/bmbgota/bmbgota_tb.1_bmbgota_ext/batch_4/ff_mm/ac_ol.csv Index:4
FAIL: group:ff_mm file:work/sim/bmbgota/bmbgota_tb.1_bmbgota_ext/batch_4/ff_mm/ac_ol.csv Index:9
FAIL: group:ff_mm file:work/sim/bmbgota/bmbgota_tb.1_bmbgota_ext/batch_4/ff_mm/ac_ol.csv Index:10
FAIL: group:ff_mm file:work/sim/bmbgota/bmbgota_tb.1_bmbgota_ext/batch_4/ff_mm/ac_ol.csv Index:25
FAIL: group:ff_mm file:work/sim/bmbgota/bmbgota_tb.1_bmbgota_ext/batch_4/ff_mm/ac_ol.csv Index:26
FAIL: group:ff_mm file:work/sim/bmbgota/bmbgota_tb.1_bmbgota_ext/batch_4/ff_mm/ac_ol.csv Index:27
FAIL: group:ff_mm file:work/sim/bmbgota/bmbgota_tb.1_bmbgota_ext/batch_4/ff_mm/ac_ol.csv Index:31
FAIL: group:ff_mm file:work/sim/bmbgota/bmbgota_tb.1_bmbgota_ext/batch_4/ff_mm/ac_ol.csv Index:46
FAIL: group:ff_mm file:work/sim/bmbgota/bmbgota_tb.1_bmbgota_ext/batch_4/ff_mm/ac_ol.csv Index:47
FAIL: group:tt_mm file:work/sim/bmbgota/bmbgota_tb.1_bmbgota_ext/batch_4/tt_mm/ac_ol.csv Index:12
FAIL: group:ll_mm file:work/sim/bmbgota/bmbgota_tb.1_bmbgota_ext/batch_4/ll_mm/ac_ol.csv Index:0
FAIL: group:ll_mm file:work/sim/bmbgota/bmbgota_tb.1_bmbgota_ext/batch_4/ll_mm/ac_ol.csv Index:5
FAIL: group:ll_mm file:work/sim/bmbgota/bmbgota_tb.1_bmbgota_ext/batch_4/ll_mm/ac_ol.csv Index:12
FAIL: group:ll_mm file:work/sim/bmbgota/bmbgota_tb.1_bmbgota_ext/batch_4/ll_mm/ac_ol.csv Index:15
FAIL: group:ll_mm file:work/sim/bmbgota/bmbgota_tb.1_bmbgota_ext/batch_4/ll_mm/ac_ol.csv Index:23
FAIL: group:ll_mm file:work/sim/bmbgota/bmbgota_tb.1_bmbgota_ext/batch_4/ll_mm/ac_ol.csv Index:24
FAIL: group:ll_mm file:work/sim/bmbgota/bmbgota_tb.1_bmbgota_ext/batch_4/ll_mm/ac_ol.csv Index:25
FAIL: group:ll_mm file:work/sim/bmbgota/bmbgota_tb.1_bmbgota_ext/batch_4/ll_mm/ac_ol.csv Index:27
FAIL: group:ll_mm file:work/sim/bmbgota/bmbgota_tb.1_bmbgota_ext/batch_4/ll_mm/ac_ol.csv Index:31
FAIL: group:ll_mm file:work/sim/bmbgota/bmbgota_tb.1_bmbgota_ext/batch_4/ll_mm/ac_ol.csv Index:34
FAIL: group:ll_mm file:work/sim/bmbgota/bmbgota_tb.1_bmbgota_ext/batch_4/ll_mm/ac_ol.csv Index:37
FAIL: group:ll_mm file:work/sim/bmbgota/bmbgota_tb.1_bmbgota_ext/batch_4/ll_mm/ac_ol.csv Index:42
FAIL: group:ll_mm file:work/sim/bmbgota/bmbgota_tb.1_bmbgota_ext/batch_4/ll_mm/ac_ol.csv Index:45
FAIL: group:ll_mm file:work/sim/bmbgota/bmbgota_tb.1_bmbgota_ext/batch_4/ll_mm/ac_ol.csv Index:48
FAIL: group:ff_mm file:work/sim/bmbgota/bmbgota_tb.1_bmbgota_ext/batch_1/ff_mm/ac_ol.csv Index:12
FAIL: group:ff_mm file:work/sim/bmbgota/bmbgota_tb.1_bmbgota_ext/batch_1/ff_mm/ac_ol.csv Index:13
FAIL: group:ff_mm file:work/sim/bmbgota/bmbgota_tb.1_bmbgota_ext/batch_1/ff_mm/ac_ol.csv Index:20
FAIL: group:ff_mm file:work/sim/bmbgota/bmbgota_tb.1_bmbgota_ext/batch_1/ff_mm/ac_ol.csv Index:30
FAIL: group:ff_mm file:work/sim/bmbgota/bmbgota_tb.1_bmbgota_ext/batch_1/ff_mm/ac_ol.csv Index:32
FAIL: group:ff_mm file:work/sim/bmbgota/bmbgota_tb.1_bmbgota_ext/batch_1/ff_mm/ac_ol.csv Index:35
FAIL: group:ff_mm file:work/sim/bmbgota/bmbgota_tb.1_bmbgota_ext/batch_1/ff_mm/ac_ol.csv Index:36
FAIL: group:ff_mm file:work/sim/bmbgota/bmbgota_tb.1_bmbgota_ext/batch_1/ff_mm/ac_ol.csv Index:37
FAIL: group:ff_mm file:work/sim/bmbgota/bmbgota_tb.1_bmbgota_ext/batch_1/ff_mm/ac_ol.csv Index:40
FAIL: group:ff_mm file:work/sim/bmbgota/bmbgota_tb.1_bmbgota_ext/batch_1/ff_mm/ac_ol.csv Index:42
FAIL: group:ff_mm file:work/sim/bmbgota/bmbgota_tb.1_bmbgota_ext/batch_1/ff_mm/ac_ol.csv Index:45
FAIL: group:ff_mm file:work/sim/bmbgota/bmbgota_tb.1_bmbgota_ext/batch_1/ff_mm/ac_ol.csv Index:46
FAIL: group:ff_mm file:work/sim/bmbgota/bmbgota_tb.1_bmbgota_ext/batch_1/ff_mm/ac_ol.csv Index:49
FAIL: group:ll_mm file:work/sim/bmbgota/bmbgota_tb.1_bmbgota_ext/batch_1/ll_mm/ac_ol.csv Index:5
FAIL: group:ll_mm file:work/sim/bmbgota/bmbgota_tb.1_bmbgota_ext/batch_1/ll_mm/ac_ol.csv Index:9
FAIL: group:ll_mm file:work/sim/bmbgota/bmbgota_tb.1_bmbgota_ext/batch_1/ll_mm/ac_ol.csv Index:18
FAIL: group:ll_mm file:work/sim/bmbgota/bmbgota_tb.1_bmbgota_ext/batch_1/ll_mm/ac_ol.csv Index:20
FAIL: group:ll_mm file:work/sim/bmbgota/bmbgota_tb.1_bmbgota_ext/batch_1/ll_mm/ac_ol.csv Index:21
FAIL: group:ll_mm file:work/sim/bmbgota/bmbgota_tb.1_bmbgota_ext/batch_1/ll_mm/ac_ol.csv Index:25
FAIL: group:ll_mm file:work/sim/bmbgota/bmbgota_tb.1_bmbgota_ext/batch_1/ll_mm/ac_ol.csv Index:28
FAIL: group:ll_mm file:work/sim/bmbgota/bmbgota_tb.1_bmbgota_ext/batch_1/ll_mm/ac_ol.csv Index:30
FAIL: group:ll_mm file:work/sim/bmbgota/bmbgota_tb.1_bmbgota_ext/batch_1/ll_mm/ac_ol.csv Index:32
FAIL: group:ll_mm file:work/sim/bmbgota/bmbgota_tb.1_bmbgota_ext/batch_1/ll_mm/ac_ol.csv Index:33
FAIL: group:ll_mm file:work/sim/bmbgota/bmbgota_tb.1_bmbgota_ext/batch_1/ll_mm/ac_ol.csv Index:36
FAIL: group:ll_mm file:work/sim/bmbgota/bmbgota_tb.1_bmbgota_ext/batch_1/ll_mm/ac_ol.csv Index:38
FAIL: group:ll_mm file:work/sim/bmbgota/bmbgota_tb.1_bmbgota_ext/batch_1/ll_mm/ac_ol.csv Index:39
FAIL: group:ll_mm file:work/sim/bmbgota/bmbgota_tb.1_bmbgota_ext/batch_1/ll_mm/ac_ol.csv Index:48
FAIL: group:ff_mm file:work/sim/bmbgota/bmbgota_tb.1_bmbgota_ext/batch_3/ff_mm/ac_ol.csv Index:0
FAIL: group:ff_mm file:work/sim/bmbgota/bmbgota_tb.1_bmbgota_ext/batch_3/ff_mm/ac_ol.csv Index:3
FAIL: group:ff_mm file:work/sim/bmbgota/bmbgota_tb.1_bmbgota_ext/batch_3/ff_mm/ac_ol.csv Index:4
FAIL: group:ff_mm file:work/sim/bmbgota/bmbgota_tb.1_bmbgota_ext/batch_3/ff_mm/ac_ol.csv Index:10
FAIL: group:ff_mm file:work/sim/bmbgota/bmbgota_tb.1_bmbgota_ext/batch_3/ff_mm/ac_ol.csv Index:11
FAIL: group:ff_mm file:work/sim/bmbgota/bmbgota_tb.1_bmbgota_ext/batch_3/ff_mm/ac_ol.csv Index:21
FAIL: group:ff_mm file:work/sim/bmbgota/bmbgota_tb.1_bmbgota_ext/batch_3/ff_mm/ac_ol.csv Index:23
FAIL: group:ff_mm file:work/sim/bmbgota/bmbgota_tb.1_bmbgota_ext/batch_3/ff_mm/ac_ol.csv Index:35
FAIL: group:ff_mm file:work/sim/bmbgota/bmbgota_tb.1_bmbgota_ext/batch_3/ff_mm/ac_ol.csv Index:39
FAIL: group:ff_mm file:work/sim/bmbgota/bmbgota_tb.1_bmbgota_ext/batch_3/ff_mm/ac_ol.csv Index:40
FAIL: group:ff_mm file:work/sim/bmbgota/bmbgota_tb.1_bmbgota_ext/batch_3/ff_mm/ac_ol.csv Index:42
FAIL: group:ff_mm file:work/sim/bmbgota/bmbgota_tb.1_bmbgota_ext/batch_3/ff_mm/ac_ol.csv Index:43
FAIL: group:ff_mm file:work/sim/bmbgota/bmbgota_tb.1_bmbgota_ext/batch_3/ff_mm/ac_ol.csv Index:47
FAIL: group:ll_mm file:work/sim/bmbgota/bmbgota_tb.1_bmbgota_ext/batch_3/ll_mm/ac_ol.csv Index:1
FAIL: group:ll_mm file:work/sim/bmbgota/bmbgota_tb.1_bmbgota_ext/batch_3/ll_mm/ac_ol.csv Index:2
FAIL: group:ll_mm file:work/sim/bmbgota/bmbgota_tb.1_bmbgota_ext/batch_3/ll_mm/ac_ol.csv Index:3
FAIL: group:ll_mm file:work/sim/bmbgota/bmbgota_tb.1_bmbgota_ext/batch_3/ll_mm/ac_ol.csv Index:5
FAIL: group:ll_mm file:work/sim/bmbgota/bmbgota_tb.1_bmbgota_ext/batch_3/ll_mm/ac_ol.csv Index:8
FAIL: group:ll_mm file:work/sim/bmbgota/bmbgota_tb.1_bmbgota_ext/batch_3/ll_mm/ac_ol.csv Index:9
FAIL: group:ll_mm file:work/sim/bmbgota/bmbgota_tb.1_bmbgota_ext/batch_3/ll_mm/ac_ol.csv Index:13
FAIL: group:ll_mm file:work/sim/bmbgota/bmbgota_tb.1_bmbgota_ext/batch_3/ll_mm/ac_ol.csv Index:14
FAIL: group:ll_mm file:work/sim/bmbgota/bmbgota_tb.1_bmbgota_ext/batch_3/ll_mm/ac_ol.csv Index:16
FAIL: group:ll_mm file:work/sim/bmbgota/bmbgota_tb.1_bmbgota_ext/batch_3/ll_mm/ac_ol.csv Index:19
FAIL: group:ll_mm file:work/sim/bmbgota/bmbgota_tb.1_bmbgota_ext/batch_3/ll_mm/ac_ol.csv Index:24
FAIL: group:ll_mm file:work/sim/bmbgota/bmbgota_tb.1_bmbgota_ext/batch_3/ll_mm/ac_ol.csv Index:27
FAIL: group:ll_mm file:work/sim/bmbgota/bmbgota_tb.1_bmbgota_ext/batch_3/ll_mm/ac_ol.csv Index:30
FAIL: group:ll_mm file:work/sim/bmbgota/bmbgota_tb.1_bmbgota_ext/batch_3/ll_mm/ac_ol.csv Index:32
FAIL: group:ll_mm file:work/sim/bmbgota/bmbgota_tb.1_bmbgota_ext/batch_3/ll_mm/ac_ol.csv Index:38
FAIL: group:ll_mm file:work/sim/bmbgota/bmbgota_tb.1_bmbgota_ext/batch_3/ll_mm/ac_ol.csv Index:41
FAIL: group:ll_mm file:work/sim/bmbgota/bmbgota_tb.1_bmbgota_ext/batch_3/ll_mm/ac_ol.csv Index:43
FAIL: group:ll_mm file:work/sim/bmbgota/bmbgota_tb.1_bmbgota_ext/batch_3/ll_mm/ac_ol.csv Index:44
FAIL: group:ll_mm file:work/sim/bmbgota/bmbgota_tb.1_bmbgota_ext/batch_3/ll_mm/ac_ol.csv Index:49
FAIL: group:ff_mm file:work/sim/bmbgota/bmbgota_tb.1_bmbgota_ext/batch_0/ff_mm/ac_ol.csv Index:3
FAIL: group:ff_mm file:work/sim/bmbgota/bmbgota_tb.1_bmbgota_ext/batch_0/ff_mm/ac_ol.csv Index:10
FAIL: group:ff_mm file:work/sim/bmbgota/bmbgota_tb.1_bmbgota_ext/batch_0/ff_mm/ac_ol.csv Index:26
FAIL: group:ff_mm file:work/sim/bmbgota/bmbgota_tb.1_bmbgota_ext/batch_0/ff_mm/ac_ol.csv Index:30
FAIL: group:ff_mm file:work/sim/bmbgota/bmbgota_tb.1_bmbgota_ext/batch_0/ff_mm/ac_ol.csv Index:35
FAIL: group:ll_mm file:work/sim/bmbgota/bmbgota_tb.1_bmbgota_ext/batch_0/ll_mm/ac_ol.csv Index:2
FAIL: group:ll_mm file:work/sim/bmbgota/bmbgota_tb.1_bmbgota_ext/batch_0/ll_mm/ac_ol.csv Index:4
FAIL: group:ll_mm file:work/sim/bmbgota/bmbgota_tb.1_bmbgota_ext/batch_0/ll_mm/ac_ol.csv Index:5
FAIL: group:ll_mm file:work/sim/bmbgota/bmbgota_tb.1_bmbgota_ext/batch_0/ll_mm/ac_ol.csv Index:8
FAIL: group:ll_mm file:work/sim/bmbgota/bmbgota_tb.1_bmbgota_ext/batch_0/ll_mm/ac_ol.csv Index:10
FAIL: group:ll_mm file:work/sim/bmbgota/bmbgota_tb.1_bmbgota_ext/batch_0/ll_mm/ac_ol.csv Index:11
FAIL: group:ll_mm file:work/sim/bmbgota/bmbgota_tb.1_bmbgota_ext/batch_0/ll_mm/ac_ol.csv Index:16
FAIL: group:ll_mm file:work/sim/bmbgota/bmbgota_tb.1_bmbgota_ext/batch_0/ll_mm/ac_ol.csv Index:19
FAIL: group:ll_mm file:work/sim/bmbgota/bmbgota_tb.1_bmbgota_ext/batch_0/ll_mm/ac_ol.csv Index:20
FAIL: group:ll_mm file:work/sim/bmbgota/bmbgota_tb.1_bmbgota_ext/batch_0/ll_mm/ac_ol.csv Index:21
CMRR/PSRR Specification [PEX]
Parameter |
Min (Spec. / Sim.) |
|
Max (Sim. / Spec.) |
Unit |
Checks (total/pass/fail/NaN) |
Comment |
CMRR at 10Hz |
50 / 91.282 |
|
91.774 / 150 |
dB |
5/100.0%/0.0%/0.0% |
|
CMRR at 10MHz |
35 / 53.266 |
|
56.93 / 90 |
dB |
5/100.0%/0.0%/0.0% |
|
PSRR+ at 10Hz |
40 / 94.479 |
|
96.382 / 130 |
dB |
5/100.0%/0.0%/0.0% |
|
PSRR+ at 10MHz |
35 / 50.122 |
|
54.162 / 70 |
dB |
5/100.0%/0.0%/0.0% |
|
PSRR- at 10Hz |
40 / 84.455 |
|
84.801 / 120 |
dB |
5/100.0%/0.0%/0.0% |
|
PSRR- at 10MHz |
5 / 9.917 |
|
11.618 / 20 |
dB |
5/100.0%/0.0%/0.0% |
|
CMRR/PSRR Specification (Monte Carlo) [PEX]
Parameter |
Min (Spec. / Sim.) |
|
Max (Sim. / Spec.) |
Unit |
Checks (total/pass/fail/NaN) |
Comment |
CMRR at 10Hz |
50 / 65.855 |
|
100.286 / 150 |
dB |
1250/100.0%/0.0%/0.0% |
|
CMRR at 10MHz |
35 / 51.61 |
|
62.915 / 90 |
dB |
1250/100.0%/0.0%/0.0% |
|
PSRR+ at 10Hz |
40 / 63.984 |
|
111.381 / 130 |
dB |
1250/100.0%/0.0%/0.0% |
|
PSRR+ at 10MHz |
35 / 48.956 |
|
57.234 / 70 |
dB |
1250/100.0%/0.0%/0.0% |
|
PSRR- at 10Hz |
50 / 82.748 |
|
87.629 / 120 |
dB |
1250/100.0%/0.0%/0.0% |
|
PSRR- at 10MHz |
5 / 9.828 |
|
11.856 / 20 |
dB |
1250/100.0%/0.0%/0.0% |
|
Slew-Rate/Offset Specification [PEX]
Parameter |
Min (Spec. / Sim.) |
|
Max (Sim. / Spec.) |
Unit |
Checks (total/pass/fail/NaN) |
Comment |
Input Offset |
-0.0 / 0.0 |
|
0.0 / 0.0 |
mV |
5/100.0%/0.0%/0.0% |
|
Slew-Rate (Positive) |
10.0 / 14.26 |
|
17.427 / 30.0 |
MV/s |
5/100.0%/0.0%/0.0% |
|
Slew-Rate (Negative) |
-30.0 / -21.365 |
|
-16.806 / -10.0 |
MV/s |
5/100.0%/0.0%/0.0% |
|
Slew-Rate/Offset Specification (Monte Carlo) [PEX]
Parameter |
Min (Spec. / Sim.) |
|
Max (Sim. / Spec.) |
Unit |
Checks (total/pass/fail/NaN) |
Comment |
Input Offset |
-10.0 / -3.994 |
|
2.269 / 10.0 |
mV |
1250/100.0%/0.0%/0.0% |
|
Slew-Rate (Positive) |
10.0 / 13.898 |
|
17.776 / 30.0 |
MV/s |
1250/100.0%/0.0%/0.0% |
|
Slew-Rate (Negative) |
-30.0 / -21.822 |
|
-16.571 / -10.0 |
MV/s |
1250/100.0%/0.0%/0.0% |
|
Noise Specification [PEX]
Parameter |
Min (Spec. / Sim.) |
|
Max (Sim. / Spec.) |
Unit |
Checks (total/pass/fail/NaN) |
Comment |
Input Noise at 10Hz |
0.0 / 0.944 |
|
1.033 / 10.0 |
uV/sqrt(Hz) |
5/100.0%/0.0%/0.0% |
|
Input Noise at 10MHz |
0.0 / 0.046 |
|
0.05 / 1.0 |
uV/sqrt(Hz) |
5/100.0%/0.0%/0.0% |
|
THD Specification [PEX]
Parameter |
Min (Spec. / Sim.) |
|
Max (Sim. / Spec.) |
Unit |
Checks (total/pass/fail/NaN) |
Comment |
THD |
0 / 0.135 |
|
0.177 / 0.3 |
% |
5/100.0%/0.0%/0.0% |
|
THD Specification (Monte Carlo) [PEX]
Parameter |
Min (Spec. / Sim.) |
|
Max (Sim. / Spec.) |
Unit |
Checks (total/pass/fail/NaN) |
Comment |
THD |
0 / 0.125 |
|
0.195 / 0.3 |
% |
1250/100.0%/0.0%/0.0% |
|