ASIC Artefacts

5 V ADC

8 bit ADC.

sar8


🔗 Schematics

LVS

LVS-state: Netlists match uniquely.

🔗 LVS-report

SPECIFICATIONS

Tranisent Specification

Parameter Min (Spec. / Sim.) Max (Sim. / Spec.) Unit Checks (total/pass/fail/NaN) Comment

Tranisent Specification [PEX]

Parameter Min (Spec. / Sim.) Max (Sim. / Spec.) Unit Checks (total/pass/fail/NaN) Comment

PERFORMANCE CHARACTERISTICS

Transient Performance

xyplot_t_samplesample_valgroup_('tt',-2),('ff',-2),('ss',-2),('ll',-2),('hh',_-2)__d0f71e1bedefb49274921b4491188e23

xyplot_sample_valinlgroup_('tt',-2),('ff',-2),('ss',-2),('ll',-2),('hh',_-2)__d0f71e1bedefb49274921b4491188e23

xyplot_t_samplesample_valv(temperature)('tt',-2)__d0f71e1bedefb49274921b4491188e23
Corner: tt

xyplot_sample_valinlv(temperature)('tt',-2)__d0f71e1bedefb49274921b4491188e23
Corner: tt

Transient Performance [PEX]

xyplot_t_samplesample_valgroup_('tt',-2),('ff',-2),('ss',-2),('ll',-2),('hh',_-2)__8e27750b13e02196f6db101d362769cc

xyplot_sample_valinlgroup_('tt',-2),('ff',-2),('ss',-2),('ll',-2),('hh',_-2)__8e27750b13e02196f6db101d362769cc

xyplot_t_samplesample_valv(temperature)('tt',-2)__8e27750b13e02196f6db101d362769cc
Corner: tt

xyplot_sample_valinlv(temperature)('tt',-2)__8e27750b13e02196f6db101d362769cc
Corner: tt